Field of the Disclosure
The present disclosure relates to the technical field of producing an active matrix organic light emitting diode display, and in particular, to a low temperature polycrystalline silicon field effect thin film transistor (TFT) array substrate and a method of producing the same, and a display apparatus including the low temperature polycrystalline silicon field effect thin film transistor array substrate.
Description of the Related Art
In comparison with a liquid crystal display, an organic light emitting diode display has advantages of high response speed, low weight, flexibility and wide visual angle. Further, an active matrix organic light emitting diode (AMOLED) has advantages of small driving current and low power consumption and thus is suitable for a high resolution display. Architecture of the active matrix organic light emitting diode may be driven by amorphous silicon, polycrystalline silicon, oxide semiconductor or organic thin film transistor. In an example, the amorphous silicon or the organic thin film transistor has low carrier mobility and low driving current, and thus the voltage required for driving high brightness organic light emitting diodes becomes high and its device also has a large dimension. The low temperature polycrystalline silicon has the mobility of up to 100 cm2/V-s. Its high current characteristics just conform to strict requirements for the organic light emitting diodes. The organic light emitting diode has a long lifetime due to its low operation voltage and high density driving architecture. Distinguished from the voltage driving mode of the conventional liquid crystal display, the current driving architecture required for driving the organic light emitting diodes is special and a compensation circuit for improving the uniformity of the gray scales and panel is also needed. And 2˜6 thin film transistors are often needed in one pixel. The high density layout of the low temperature polycrystalline silicon allows the organic light emitting diode panel with high brightness and high display quality to be produced more easily. Currently, most of the commercially available AMOLEDs use the low temperature polycrystalline silicon field effect thin film transistor array substrate.
FIG. 1 is a schematic view of the conventional low temperature polycrystalline silicon field effect thin film transistor array substrate. In the conventional process for producing the low temperature polycrystalline silicon field effect thin film transistor array substrate, typically 8-9 patterning processes are needed, causing the production process to become more complex. With reference to FIGS. 2A˜2G, the conventional process for producing the low temperature polycrystalline silicon field effect thin film transistor array substrate shown in FIG. 1 will be explained below.
As illustrated in FIG. 2A, a silicon nitride (SiN) film and a silicon dioxide (SiO2) film are deposited sequentially on an entire insulation substrate 1 by plasma enhanced chemical vapor deposition (PECVD), to form a buffer layer 2 composed of the silicon nitride and the silicon dioxide. Next, an amorphous silicon (α-Si) film is formed on the buffer layer 2 by PECVD or other chemical or physical vapor deposition processes. By means of Excimer Laser Annealing (ELA) or solid phase crystallization (SPC), the α-Si may be crystallized into a polycrystalline silicon film. Then, a pattern in a layer of photo resist is formed on the polycrystalline silicon film by the conventional patterning process. With the layer of photo resist used as an etching barrier layer, the portion of the polycrystalline silicon film that is not shielded is etched by plasma to form a polycrystalline silicon active layer 4 and a polycrystalline silicon storage capacitor 3. Low concentration ion implantation is carried out in the transistor channel in the polycrystalline silicon active layer 4 by ion implantation process, so as to form a conductive channel required for the thin film transistor in the polycrystalline silicon active layer 4.
As illustrated in FIG. 2B, a layer of photo resist 5 composed of photo resist material is formed on the polycrystalline silicon active layer 4 by a patterning process, so as to protect the polycrystalline silicon active layer 4 from being implanted with ions. The polycrystalline silicon storage capacitor 3 that is not protected by the layer of photo resist is implanted with high concentration ions. In this way, the polycrystalline silicon storage capacitor 3 is converted into low resistance doped polycrystalline silicon film. During the subsequent processes as shown in FIGS. 2C-2G, as a second polar plate of a capacitor composed of a gate insulation layer and a gate metal film is only formed on the polycrystalline silicon storage capacitor 3, FIGS. 2C-2G do not show a single lithographic process after the polycrystalline silicon storage capacitor 3 is formed, i.e., the lithographic process for forming the second polar plate of the capacitor 3, any longer.
As illustrated in FIG. 2C, the layer of photo resist 5 on the polycrystalline silicon active layer 4 is removed by a photo resist peeling process, a SiO2 film or a composite film of SiO2 and SiN is deposited by PECVD and the gate insulation layer 6 is formed on the polycrystalline silicon storage capacitor 3, the polycrystalline silicon active layer 4 and the entire buffer layer 2. One or more low resistance metal material film is deposited on the gate insulation layer 6 by physical vapor deposition process such as magnetron sputtering, and a gate electrode 7 is formed by a lithographic process. The gate electrode 7 is used as an ion implantation barrier layer to dope the polycrystalline silicon active layer 4 with ions and thus to form low resistance source electrode and drain electrode contact areas on the polycrystalline silicon active layer area that is not blocked by the gate electrode.
As illustrated in FIG. 2D, on the entire surface including the gate electrode 7, the SiO2 film and the SiN film are deposited sequentially by PECVD to form an interlayer insulation layer 8. The interlayer insulation layer 8 is etched by patterning and etching processes to form a source electrode contact hole 15 and a drain electrode contact hole 16.
As illustrated in FIG. 2E, one or more low resistance metal film is deposited by magnetron sputtering on the interlayer insulation layer 8 and the source electrode contact hole 15 and the drain electrode contact hole 16. A source electrode 9 and a drain electrode 10 are formed by patterning and etching processes. The source electrode 9 and the drain electrode 10 comes in ohm contact with the polycrystalline silicon active layer 4 through the contact holes 15, 16. The doping ions in the polycrystalline silicon active layer 4 are activated by rapid thermal annealing or heat treatment furnace annealing to form an efficient conductive channel in the polycrystalline silicon active layer 4 under the gate electrode 7.
As illustrated in FIG. 2F, a layer of SiN film is deposited on an entire surface including the source electrode 9 and the drain electrode 10 by PECVD and a passivation layer 11 including a via hole 17 is formed by patterning and etching processes. By means of hydrogenation process by rapid thermal annealing or heat treatment furnace annealing, the defects in the interior and the interface of the polycrystalline silicon active layer 4 can be repaired. Again, by the patterning process, an organic planarization layer 18 with the same via hole as the via hole 17 is formed above the SiN passivation layer 11 to fill recesses on the surface of a device to form a planar surface.
As illustrated in FIG. 2G, a layer of transparent conductive film is deposited above the organic planarization layer 18 and the via hole 17 by magnetron sputtering and the transparent conductive film is etched by a lithographic process to form a pixel electrode 12 in a pixel area above the via hole 17 and a part of the organic planarization layer 18. Then, a layer of photo sensitive organic material similar to the organic planarization layer 18 is coated on the organic planarization layer 18 and the pixel electrode 12. Partial area of the pixel electrode 12 is exposed by the last patterning process to form a pixel definition layer 13 shown in FIG. 1. The pixel definition layer 13 covers the organic planarization layer 18 and the partial area of the pixel electrode 12.
As discussed above, the low temperature polycrystalline silicon field effect thin film transistor array substrate shown in FIG. 1 is formed by at least 8-9 lithographic processes, including forming the polycrystalline silicon active layer, the doping storage capacitor, the gate electrode, the interlayer insulation layer contact hole, the source electrode and the drain electrode, the passivation layer via hole, the planarization layer, the pixel electrode and the pixel definition layer respectively by lithographic processes. It will cause a long process time and a low yield. In this way, the production process becomes complex and the production cost becomes high.